The present invention relates to a phase control circuit appropriately used in a resonant switching regulator, etc. which adopts soft switching so as to reduce switching loss, and the resonant switching regulator provided with the phase control circuit.
Conventionally, as for a phase control circuit for a switching regulator, a structure disclosed in U.S. Pat. No. 5,291,384 (Date of Patent: Mar. 1, 1994) has been known. A phase control circuit disclosed in the patent is structured so as to control a pulse width modulation (PWM) circuit which controls the phases of output signals A and B and output signals C and D, using an output pulse of an oscillation circuit.
FIG. 6 shows a block diagram of the conventional phase control circuit. In FIG. 6, an output of a switching circuit 53 is switched by a clock signal 52 outputted from an oscillator 51.
Output signals XA 54 and XB 55 of the switching circuit 53 have opposite polarities, and are inputted to output circuits A 56 and B 57, respectively. Delay circuits 56A and 57A are provided in the output circuits A 56 and B 57, respectively, and a delay period of each of the delay circuits 56A and 57A is set by a delay set AB 58. Each of the delay circuits 56A and 57A causes a delay in the rising timing of an output signal A 59 outputted from the output circuit A 56, and in the rising timing of an output signal B 510 outputted from the output circuit B 57.
The output signal XA 54 of the switching circuit 53 is also connected to a first input terminal 512 of an XOR circuit 511. To a second input terminal 513 of the XOR circuit (exclusive OR) 511, a signal from an output terminal of a PWM latch circuit 514 is provided.
The XOR circuit 511 outputs output signals XC 515 and XD 516, and these output signals are inputted to output circuits C 517 and D 518, respectively. The output signals XC 515 and XD 516 have opposite polarities, in the same way as the foregoing output signals XA 54 and XB 55.
The output circuits C 517 and D 518 include delay circuits 517A and 518A, respectively, in the same way as the output circuits A 56 and B 57. A delay is caused in the rising timing of an output signal C 520 outputted from the output circuit C 517, and in the rising timing of an output signal D 521 outputted from the output circuit D 518, by a delay period set by a delay set CD 519.
In an error amplification circuit 522, a first reference voltage source 524 is connected to a positive input terminal 523, and a monitor signal voltage 526 is inputted to a negative input terminal 525. The voltages at the positive input terminal 523 and at the negative input terminal 525 are compared and their difference is amplified to form an error signal 527, which is inputted to two comparators 528 and 538.
To a positive input terminal 529 of the PWM comparator 528, one of the comparators, the error signal 527, which is an output signal of the error amplification circuit 522, is inputted. To a negative input terminal 530 of the PWM comparator 528, a ramp wave signal 532 formed according to the clock signal 52 is inputted via a level shift circuit 531. The PWM comparator 528 compares the foregoing two signals and outputs a first error detection signal 533.
The first error detection signal 533 is inputted to a set terminal 534 of the PWM latch circuit 514 as an input signal only when the clock signal 52 is in a low level. In such a set input, the polarity of each of the output signals C 520 and D 521 is reversed, compared with the case where the PWM latch circuit 514 is in a reset state.
The PWM latch circuit 514, once set, keeps the output low until being reset by the clock signal 52. Besides, in the PWM latch circuit 514, while a signal is inputted to a reset terminal 535, no signal is applied to the set terminal 534, and the output of the PWM latch circuit 514 is always in a high level.
Another comparator 538, to which the error signal 527 as an output of the error amplification circuit 522 is inputted, compares a voltage level of the error signal 527 and a voltage level (for example, 1V) of a second reference voltage source 536. When the voltage level of the error signal 527 is lower than the voltage level of the second reference voltage source 536, the comparator 538 outputs a second error detection signal 537 (in a high level).
The second error detection signal 537 has a function to apply no signal according to the clock signal 52 to the reset terminal 535 of the PWM latch circuit 514. Hence, when the second error detection signal 537 is outputted, if a signal is inputted to the set terminal 534 of the PWM latch circuit 514 even just once, the output of the PWM latch circuit 514 is kept low unless the second error detection signal 537 is cancelled (becomes low).
FIG. 7 shows a resonant switching regulator which controls regulator output voltage using the phase control circuit shown in FIG. 6. FIG. 8 shows a timing chart of the circuit shown in FIG. 7.
The output signals A 59, B 510, C 520, and D 521 of the phase control circuit are inputted as control signals for switches A 639, B 640, C 641, and D 642, respectively, of the resonant switching regulator. Here, the switches A 639 and D 642, and the switches B 640 and C 641 are paired respectively so as to transmit a current through a primary 643 and supply power to a secondary 644 of a transformer 650.
When this phase control circuit is used as a controller for the resonant switching regulator, the first reference voltage source 524 is connected to the positive input terminal 523 of the error amplification circuit 522. To the negative input terminal 525 of the error amplification circuit 522, the monitor signal voltage 526, formed by dividing the voltage of a regulator output terminal 648 to which power is supplied from the secondary 644 of the transformer 650, is supplied.
Here, in order to make the voltages inputted to the both input terminals of the error amplification circuit 522 equal, the phase control circuit controls the switching phases of the paired switches A 639, B 640, C 641, and D 642. Then, the phase control circuit adjusts power supply to the secondary 644 of the transformer 650, so that the voltage of the regulator output terminal 648 comes to have a desired voltage level set by the error amplification circuit 522, and thus a feedback control is applied in a system.
When the voltage level of the monitor signal voltage 526 is much lower than the reference voltage of the first reference voltage source 524 of the error amplification circuit 522, no high signal is applied to the set terminal 534 of the PWM latch circuit 514. Therefore, the output of the PWM latch circuit 514 becomes high. Here, the output signals of the paired output circuits have the same polarity, and the switching phases of the paired switches in the resonant switching regulator become 0 degree. Under these conditions, power is supplied to the secondary 644 of the transformer 650, except during dead time, which is a delay period.
When the voltage level of the monitor signal voltage 526 is much higher than the reference voltage of the first reference voltage source 524 of the error amplification circuit 522, the second error detection signal 537 is outputted. So no high signal is applied to the reset terminal 535 of the PWM latch circuit 514, and if a signal in a high level is inputted to the set terminal 534 even just once during this period, the output of the PWM latch circuit 514 becomes low. Here, the output signals of the paired output circuits come to have opposite polarities, and the switching phases of the paired switches in the resonant switching regulator become 180 degrees. In this situation, power is not supplied to the secondary 644 of the transformer 650.
When the voltage level of the monitor signal voltage 526 is close to the voltage level of the reference voltage of the first reference voltage source 524 of the error amplification circuit 522, according to the comparison by the PWM comparator 528, a signal is supplied to the set terminal 534 of the PWM latch circuit 514.
However, the sampling period for performing the phase control in the resonant switching regulator and the controlling transmission time of the transformer 650 in accordance with the voltage of the regulator output terminal 648 is only when the clock signal 52 of the oscillator 51 is in a low level.
However, the conventional circuit has the following problems. When the voltage level of the error signal 527 as an output signal of the error amplification circuit 522 varies from close to the minimum voltage of the ramp wave signal 532 formed according to the clock signal 52 to the voltage level of the second reference voltage source 536, the period in which the phases of the paired switches can vary is described as follows.
from 180xe2x80x94(Dutyxc3x97180) degrees to 180 degrees
(Duty=clock signal width÷oscillation cycle)
Here, since there is a period during which the voltage cannot be controlled (the period when the clock signal 52 is in a high level) although power is supplied to the secondary 644 of the transformer 650, the phase change switches logically, and linearity in phase deviation cannot be obtained. That is, the periods in which the paired output signals are simultaneously in a high level switch logically (discretely) in the intervals between when the pulse of the clock signal 52 falls and when the pulse rises again. This is because no signal is applied to the set terminal 534 of the PWM latch circuit 514 when the clock signal 52 is in a high level.
In other words, when the conventional circuit is used as a controller for a resonant switching regulator, in a period during which an input signal to the set terminal 534 cannot be inputted, the output of the PWM latch circuit 514 is high, so the input signals of the paired switches have the same polarity. As a result, a current is transmitted through the primary 643 of the transformer 650, and thus power is supplied to the secondary 644. Here, the switching phases of the paired switches become 180xe2x80x94(Dutyxc3x97180) degrees.
In the circuit shown in FIG. 7, the ramp wave signal 532 is level-shifted to 1V and inputted to the PWM comparator 528. In the comparator 538, which has a function to apply no signal to the reset terminal 535 of the PWM latch circuit 514, the comparison reference voltage is also set at 1V.
With this structure, if the minimum voltage of the ramp wave signal 532 is 0V, when the voltage level of the error signal 527 outputted from the error amplification circuit 522 becomes lower than the minimum voltage of the ramp wave signal 532, no signal is applied to the reset terminal 535 of the PWM latch circuit 514. Then, the polarities of the input signals of the paired switches in the resonant switching regulator are reversed, and power supply to the secondary 644 of the transformer 650 is stopped. Here, the switching phases of the paired switches become 180 degrees.
In this manner, since the switching phase jumps from 180xe2x80x94(Dutyxc3x97180) degrees to 180 degrees, linearity in phase deviation (that is, responsiveness) cannot be obtained, requiring time to stabilize the voltage at the regulator output terminal 648.
To solve such a problem, there is a method to narrow the width of the clock signal 52. However, since the oscillation frequency of the clock signal 52 is determined (set) by a load connected to the secondary 644 of the transformer 650 in the resonant switching regulator, it is desirable to set the operation range of the oscillation frequency wide so as to achieve versatility. When this is the case, the width of the clock signal 52 varies in a wide range according to the operation range of the oscillation frequency.
Since the range of phase deviation in which output linearity cannot be obtained is determined by a duty, as long as the oscillation frequency varies and the width of the clock signal 52 varies according to the variation of the oscillation frequency, the phase range in question does not vary. However, the time range in which output linearity cannot be obtained becomes greater with the decrease of the oscillation frequency.
As another countermeasure, there is a method to set the delay period of an output circuit greater than the width of the clock signal 52. During the delay period, all the switches in the resonant switching regulator do not conduct, which means dead time. Thus, since power is not supplied originally, there is no need to sample the voltage of the regulator output terminal 648.
However, since the delay period is provided so as to charge and discharge parasitic capacitors in the switches by resonance and to decrease switching loss, the delay period cannot be always set greater than the width of the clock signal 52 determined by a load.
There is another problem when the second error detection signal 537 is outputted. In this case, since the polarities of the input signals of the paired switches in the resonant switching regulator are reversed, a current is not transmitted through the primary 643 of the transformer 650, and thus power is not supplied to the secondary 644.
Here, the input signals of the switches which are not originally paired have the same polarity. If each switch has an identical parasitic capacitor, the delay in each output circuit is also set identical in many cases. If the delay period is identical and the second error detection signal 537 is outputted, the conduction start timings of the switches which are not originally paired coincide.
When the paired switches operate in phase, a current flows through the primary 643 of the transformer 650 and the switches are not subjected to stress so much. However, if the voltage of a regulator input terminal 646 is high and the conduction start timings of the switches which are not originally paired coincide when the transformer 650 is not in a transmission state, there is no current-flow path and excessive voltage is applied across the switches, so the switches are subjected to substantial stress momentarily. Therefore, the foregoing conventional switching regulator has a problem that the switches are easily deteriorated over time, failing to ensure stabilized operation for a long time.
It is therefore an object of the present invention to provide a phase control circuit which can stabilize voltage control when used in a switching regulator, and a switching regulator using such a phase control circuit.
To achieve the foregoing object, a phase control circuit in accordance with the present invention is structured so as to include:
a first pair of output stages for generating a first output signal and a second output signal based on a clock signal so that the first and the second output signals are pulse signals having opposite polarities;
a second pair of output stages, reset by a reset signal, for generating a third output signal and a fourth output signal which have phases controlled with respect to the first and the second output signals by the first and the second output signals respectively and also by a set signal produced based on a control signal, so that the third and the fourth output signals are pulse signals having opposite polarities;
first delay means for delaying, before output, the rising of the first through the fourth output signals; and
delay pulse means for generating a delay pulse based on low level periods of the delayed first and second output signals, and for resetting the second pair of output stages using the delay pulse as the reset signal.
In the foregoing phase control circuit, it is desirable that a delay period is provided so as to reduce switching loss in a resonant switching regulator to which the first through the fourth output signals are connected.
It is also desirable that the foregoing control signal is a monitor signal in accordance with an output voltage of a resonant switching regulator to which the first through fourth output signals are connected.
According to the foregoing structure, a pulse signal whose pulse width is equal to a delay period of the first delay means is used as a reset signal for the second pair of output stages. With this structure, the second pair of output stages is reset, for example, in dead time of the resonant switching regulator. Therefore, the phase deviations of the third and the fourth output signals can be controlled from 0 degree to 180 degrees with respect to the first and the second signals, respectively, without being influenced by the variation in the frequency of the clock signal, obtaining linearity, that is, responsiveness.
Consequently, since linearity in phase deviation, that is, responsiveness, can be obtained in the foregoing structure, when using the foregoing structure in, for example, a resonant switching regulator, satisfactory voltage control can be achieved in the resonant switching regulator.
It is desirable that the phase control circuit further includes blocking means for blocking an input of a set signal to the second pair of output stages in a reset state, based on the delay pulse.
According to the foregoing structure, by providing the blocking means, a set signal is prevented from being inputted to the second pair of output stages during a reset period. Therefore, the phase deviations of the third and the fourth output signals with respect to the first and the second signals can be ensured, respectively, which can further stabilize voltage control.
It is desirable that the phase control circuit further includes second delay means for further delaying the third and the fourth output signals according to a period of a delay pulse.
According to the foregoing structure, in the case of using the foregoing structure in a resonant switching regulator, when the phase deviations of the third and the fourth output signals with respect to the first and the second signals are, for example, about 180 degrees, respectively, the first output signal and the third output signal come to be in phase.
Here, the simultaneous turning on of a first switch and a third switch among a first through a fourth switches which are provided in the resonant switching regulator and driven by the first through the fourth output signals, respectively, can be avoided by a delay produced by the second delay means.
In this manner, the foregoing structure can prevent excessive voltage from being applied to the first and the third switches, reducing stress to the switches. Consequently, the life of the switches can be prolonged, and thus, the operation of the resonant switching regulator can be stabilized and its operation life can be prolonged.
It is desirable that the phase control circuit further includes comparison means for detecting a control signal, so as to set all the first through the fourth output signals to a low level when the control signal becomes higher than a predetermined value.
According to the foregoing structure, in the case of using the foregoing structure in a resonant switching regulator, when an output voltage of the resonant switching regulator exceeds a tolerable value and the control signal based on the output voltage becomes higher than a predetermined value, the comparison means can stop the operation of the resonant switching regulator. Therefore, the foregoing structure can prevent the resonant switching regulator from getting out of control, and prevent a peripheral device from being damaged by the out-of-control resonant switching regulator.
It is desirable that, in the phase control circuit, when cancelling the low level setting for each output signal, the comparison means cancels the low level settings for the first and the second output signals, and after a delay period, the comparison means cancels the low level settings for the third and the fourth output signals.
According to the foregoing structure, in the case of using the foregoing structure in, for example, a resonant switching regulator, when cancelling the low level settings for all the output signals, the low level settings for the first and the second output signals are cancelled, and after a delay period, the low level settings for the third and the fourth output signals are cancelled. Therefore, this structure can avoid the simultaneous turning on of the switches causing a primary of a transformer of the resonant switching regulator not to conduct.
Thus, when using the foregoing structure in a resonant switching regulator, stress applied to the switches in the resonant switching regulator can be reduced. Consequently, the operation of the resonant switching regulator can be stabilized and its operation life can be prolonged.
To achieve the foregoing object, a switching regulator in accordance with the present invention is structured so as to include:
a first half bridge circuit including a first switch and a second switch, connected in series, which are turned on/off according to a high/low signal;
a second half bridge circuit including a third switch and a fourth switch, connected in series, which are turned on/off according to a high/low signal;
a transformer whose primary is connected to the first and the second half bridge circuits;
a resonant circuit, connected between the first and the second half bridge circuits in series with the primary of the transformer, for soft switching so as to decrease switching loss;
a rectifier circuit connected to a secondary of the transformer;
a control signal generator circuit for generating a control signal to feed back and control an output from the rectifier circuit, based on the output; and
a phase control circuit for controlling the turning on/off of the first through the fourth switches,
the phase control circuit including:
a first pair of output stages for generating a first output signal and a second output signal based on a clock signal so that the first and the second output signals are pulse signals having opposite polarities;
a second pair of output stages, reset by a reset signal, for generating a third output signal and a fourth output signal which have phases controlled with respect to the first and the second output signals by the first and the second output signals respectively and also by a set signal produced based on a control signal, so that the third and the fourth output signals are pulse signals having opposite polarities;
first delay means for delaying, before output, the rising of the first through the fourth output signals; and
delay pulse means for generating a delay pulse based on low level periods of the delayed first and second output signals, and for resetting the second pair of output stages using the delay pulse as the reset signal, and
the first through the fourth switches of the switching regulator being respectively connected to the first through the fourth output signals of the phase control circuit.
According to the foregoing structure, by using the foregoing phase control circuit, switching loss of the resonant circuit can be reduced by applying a delay. Besides, the phase deviations in the first and the second half bridge circuits can be controlled from 0 degree to 180 degrees, without being influenced by the variation in the frequency of the clock signal, obtaining linearity, that is, responsiveness.
As a result, since linearity in phase deviation of the switches, that is, responsiveness, can be obtained in the foregoing structure, satisfactory voltage control can be achieved for output.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.